Syntest

	SynTest Technologies, Inc. develops intellectual property (IP) for advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) applications including, logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, and silicon debug and diagnosis. SynTest tools improve electronic design’s quality and reduce the overall design and test costs (Read More).

Products:

RobustScan™ - Framework for Soft-Error Protection

RobustScan™ provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardenedcombinational- cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan™ can be used with scan chains inserted using third-party tools; it can be linked to third-party’s SER analysis programs and is fully compatible with SynTest’s existing DFT tools for test, debug, and diagnosis (Read More).

DFT- PRO Plus™ - A Comprehensive Package of DFT Tools

DFT-PRO Plus ™ offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow. This gives the user the freedom to choose any commercially available logic and scan synthesis tools from vendors like Cadence, Incentia, Magma, Mentor, Synopsys or Synplicity and enables a one-pass RTL to GDSII synthesis flow. It also eases overall design floor planning (Read More).

VirtualScan™ and UltraScan™ - Tool Suite for Compression Scan Synthesis and ATPG

VirtualScan™ is SynTest's solution to combat this increase in test data volume and test cycle volume. With VirtualScan™ an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins. An evaluation on a 2-million gate design using VirtualScan™ showed a 22x reduction in test time. Further, the static and dynamic compaction capabilities of SynTest's powerful ATPG tool help reduce pattern sizes, leading to overall reduction in test costs (Read More).

UltraScan™ is SynTest's solution to reduce test time 50x to 500x. It is used along with VirtualScan™ to reduce the overall test cost. It reduces test time and data volume for all scan designs with ATPG compression structures offered by VirtualScan™. It achieves pin reduction through proprietary TDDM/ TDM circuitry. UltraScan™ also delivers better delay fault coverage for high-speed I/O pads on the device. Hardware overhead is predictable & low. VirtualScan™ and UltraScan™ provide a smooth migration into existing scan ATPG flow and also provide diagnosis support (Read More).

TurboBIST™ - Built-in Self-Test

TurboBIST™ family of products from SynTest Technologies, Inc. includes tools for logic (TurboBIST™ - Logic) and memory (TurboBIST™ - Memory) (SRAM, ROM, DRAM and CAM) built-in self-test. These tools synthesize the BIST logic surrounding functional logic and memory blocks, including IP cores from third party suppliers, and automatically generate the test patterns needed to provide very high fault coverage testing of complete complex system-on-silicon chips. TurboBIST-Logic generates synthesizable RTL blocks as well as script files, which can be used with tools from leading EDA vendors for logic simulation, synthesis and static timing analysis (Read More).

TurboBIST™ - Memory Automatically generates classical or user configurable test pattern sets, the tool supports embedded SRAMs, ROMs, SDRAMs and CAMs and outputs Verilog/VHDL synthesizable RTL code (Read More).

TurboFault™ - Fault Simulation

TurboFault™ combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate level, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will also read Standard Delay Format (SDF) timing files (Read More).

TurboCheck™ - Testability Analysis

TurboCheck™ is a Testability Analyzer and Test Assistant for both RTL (Register-Transfer-Level) and gate-level digital designs. TurboCheck analyzes the testability of sequential circuits and assists the designer in selecting test solutions that are most likely to improve the circuit's final fault coverage. TurboCheck operates on non-scan, partial-scan, or full-scan circuits. Because it is a static tool operating on the topology of the circuit, no vectors are needed for the analysis (Read More).

TurboScan™ - Scan Synthesis and ATPG

TurboScan™ is an advanced full-scan test suite. It includes a Scan Synthesizer (optional) and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce a very compact test pattern set. TurboScan is designed to reduce product defect level and save test costs (Read More).

TurboBSD™ - Boundary Scan

TurboBSD™ is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns. All these tasks are fully automated by the tool, making boundary scan design a straightforward process (Read More).

TurboDFT™ - Integration Tool Suite

TurboDFT™ contains a suite of very useful and powerful DFT integration tools. TurboDFT allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors. Rtlmsdb scripts and commands are provided for allowing users to automatically stitch DFT cores with or without boundary-scan control. Thus, TurboDFT brings "Ease of integration" benefit and eliminates the tedious, error-prone manual stitching process (Read More).

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