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POWER AWARE DESIGN
A seminar sponsored by Calypto Design Systems and AST
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SESSIONS:
Executive Session: Managing and Implementing Power Aware Design for Digital SoCs
Part I: Tom Sandoval, CEO of Calypto Design Systems
We will discuss how to drive Power Aware Design into the mindset of an SoC development team and some of the design elements that should be incorporated into a Power Aware Design engineering culture.
Part II: Anmol Mathur, Ph.D., CTO of Calypto Design Systems
We will discuss the techniques to address power at different levels of abstractions in the design process and the role that emerging power formats are playing in enabling a Power Aware Design flow.
Technical Session: Sequential Optimization Techniques for Power Aware Design
Part I: We will provide an overview of sequential optimization techniques that optimize design power by changing the behavior of the design in time, with specific focus on sequential clock gating and the use of PowerPro CG for dynamic power optimization.
Part II: We will discuss the different power modes being provided in memory IP to reduce memory dynamic and leakage power. In addition, we will provide an overview of PowerPro MG – a tool that automates sequential memory gating and generation of sleep mode controllers for memories.
AGENDA:
08:30- 09:30 Registration
09:30- 09:45 AST Welcome
09:45 -10:15 Calypto Introduction
10:15- 11:30 Calypto Executive Session
11:30- 12:30 Calypto Technical Session Part I
12:30- 13:30 Lunch
13:30- 14:30 Calypto Technical Session Part II
14:30- 14:45 Wrap-Up
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