2009

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Advanced Semiconductor Technology Ltd. (AST) is one of the first companies in Israel to implement a 40nm design*.
Raanana, Israel -- September 21, 2009 -- Advanced Semiconductor Technology Ltd. (AST) a leading independent  ASIC design house and total solution provider, today announced  its first 40nm design win. The design is implemented for a local Israeli startup and is a complex SoC design.

This design win marks a significant step toward being a leading independent ASIC design house in Israel with complete ASIC solutions for the Israeli fabless companies.
“We are very proud to be one the first and among the select few ASIC companies in Israel to implement a 40nm design”, stated Eli Geva Director of ASIC Operations at AST. “Proven track record  in advanced technology ASIC Design demonstrates our capability to handle complicated SoC designs” he added.
“By using the most advanced Synopsys ICC flow, AST is now capable to support the most complicated designs with the most advanced technologies”, stated Chen Eyal, ASIC Engineering Manager at AST.
*Tape-out planned for December 2009
About AST
Advanced Semiconductor Technologies (AST) was established in 1986 as the first independent Application Specific Integrated Circuits (ASIC) Design Center in Israel.
In the following years, AST has become the Israel Representative of major ASIC vendors as well as Electronic Design Automation (EDA) and Application Specific Standard Products (ASSP) companies.
Today, AST serves as a focal point in the Israeli market for ASIC Design Services and Supply, Advanced Electronic Components for Networking, Image Processing, LCD Displays and DSP Boards and Modules and state of the art Electronic Design Automation tools. AST represents a group of world class companies in the areas of ASIC, EDA and Application Specific Standard Products.
AST’s  team of highly skilled Sales and Application Engineers combines over 150 years of experience  providing Turn-Key services as well as on site support and consulting, in the areas of ASIC and FPGA Design, EDA and Configuration Management (CM) and other Design and Development. 
 

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AST wins the 9th Annual SNUG Israel Technical Committee  Special Award ! 
 
AST’s paper “Constraints Management Toolkit (CMT) for Synopsys Flow”  won the 9th Annual SNUG Israel Special Award.  The paper was presented by our Engineering Manager, Mr. Chen Eyal.
The presentation abstract is shown below:
 
One of the challenges of ASIC design is managing the timing constraints throughout the various steps of the design and implementation phases: from RTL through logic synthesis, P&R, Signal-Integrity and to sign-off STA.
 
The timing constraints are usually derived from the system requirements and are documented in a Device Specification. The Design Specifications has to be translated into a set of timing constraint TCL commands. The TCL scripts are used for Synthesis, P&R and Timing Sign-Off by the implementation/verification tools. The constraints are usually written and handled using long and complicated TCL scripts, and only the designer who wrote them can really understand what is going on there. Additionally, there’s no standard in the industry for design constraining, therefore designers from different groups/companies working together on the same project may have misunderstandings and/or gaps in the timing coverage of the design.
 
This paper presents a solution we developed at AST for managing ASIC design constraints. Our solution, called Constraint Management Toolset (CMT), supports the constraint management from the Design Specification through all the design implementation phases to the STA results presentation and review. We are using the highest level of data, such as oscillator frequency, duty cycle, jitter etc. directly from the Design Specification. This data is managed in Excel  worksheet template, which is very friendly and easy to update and review. CMT automatically generates TCL scripts, out of the Excel  worksheet, creating clock definitions, domain relationships, interface timing constraints, mode definitions and exceptions (false path, multi-cycle etc.). We will demonstrate in this article that our solution can handle a complete set of constraints from RTL to sign-off STA, using a single database.

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